US 11,983,116 B2
Statistic based cache pre-fetcher
Sang Wook Do, Glendale, CA (US); Wei-Yu Chen, Fremont, CA (US); and Gang Liu, Palo Alto, CA (US)
Assigned to Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Oct. 25, 2022, as Appl. No. 17/973,427.
Application 17/973,427 is a continuation of application No. PCT/US2020/030543, filed on Apr. 29, 2020.
Prior Publication US 2023/0049662 A1, Feb. 16, 2023
Int. Cl. G06F 12/0862 (2016.01); G06F 9/32 (2018.01); G06F 12/0811 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 9/321 (2013.01); G06F 12/0811 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus for pre-fetching data, the apparatus comprising:
a processor core;
pre-fetch logic circuit in communication with the processor core, the pre-fetch logic circuit being configured to:
generate cache pre-fetch requests for a program instruction identified by a program counter;
track one or more statistics with respect to the cache pre-fetch requests, including track a count of the cache pre-fetch requests that are generated for the program instruction over a recent interval, the one or more statistics including the count;
link the one or more statistics with the program counter; and
determine a pre-fetch degree of the cache pre-fetch requests for the program instruction based on the one or more statistics; and
a memory hierarchy in communication with the processor core and the pre-fetch logic circuit, the memory hierarchy comprising:
a main memory;
a hierarchy of caches; and
a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests, the memory blocks being pre-fetched from a current level in the memory hierarchy into a higher level of the memory hierarchy.