US 11,983,115 B2
System, device and method for accessing device-attached memory
Jeongho Lee, Gwacheon-si (KR); Heehyun Nam, Seoul (KR); Jaeho Shin, Gwangmyeong-si (KR); Hyodeok Shin, Seoul (KR); Younggeon Yoo, Seoul (KR); Younho Jeon, Gimhae-si (KR); Wonseb Jeong, Hwaseong-si (KR); Ipoom Jeong, Hwaseong-si (KR); and Hyeokjun Choe, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 8, 2023, as Appl. No. 18/166,244.
Application 18/166,244 is a continuation of application No. 17/380,805, filed on Jul. 20, 2021, granted, now 11,586,543.
Claims priority of application No. 10-2020-0133743 (KR), filed on Oct. 15, 2020.
Prior Publication US 2023/0185717 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0817 (2016.01); G06F 3/06 (2006.01); G06F 12/0862 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 12/0862 (2013.01); G06F 2212/602 (2013.01); G06F 2212/621 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A device connected to a host processor via a bus, the device comprising a controller configured to control access to a memory connected to the device,
wherein the device is configured to be set to a host bias mode or a device bias mode,
wherein the controller, in the host bias mode, is further configured to:
provide a first message requesting resolution of coherence to the host processor; and
send a command to the memory, before receiving a second message from the host processor in response to the first message, to prefetch first data from the memory, and
wherein the controller, in the device bias mode, is further configured to read second data from the memory without consulting the host processor about a coherence.