US 11,983,112 B2
Techniques for enhanced system performance after retention loss
Chun Sum Yeung, San Jose, CA (US); Deping He, Boise, ID (US); and Min Rui Ma, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 28, 2021, as Appl. No. 17/646,253.
Prior Publication US 2023/0205690 A1, Jun. 29, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 12/0804 (2016.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01)
CPC G06F 12/0804 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G06F 2212/1032 (2013.01); G11C 16/0483 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory system; and
a controller coupled with the memory system and configured to cause the apparatus to:
receive a power off notification from a host system;
write a first page of the memory system based at least in part on receiving the power off notification;
power off the memory system based at least in part on writing the first page of the memory system;
read the first page of the memory system as part of a power on operation; and
select a first bin associated with a first read voltage offset for one or more memory cells of the memory system using a voltage shift of the one or more memory cells based at least in part on reading the first page of the memory system.