US 11,983,071 B2
Error correction code circuit and semiconductor apparatus including the same
Seon Woo Hwang, Icheon-si (KR); Seong Jin Kim, Icheon-si (KR); and Jung Hwan Ji, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 5, 2022, as Appl. No. 17/882,123.
Claims priority of application No. 10-2022-0025976 (KR), filed on Feb. 28, 2022.
Prior Publication US 2023/0273860 A1, Aug. 31, 2023
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/108 (2013.01) 22 Claims
OG exemplary drawing
 
1. An error correction code circuit comprising:
an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data; and
a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and share substantially the same signal path in generating the first delay data and in generating the second delay data.