US 11,983,067 B2
Adjustment of code rate as function of memory endurance state metric
Kishore Kumar Muchherla, San Jose, CA (US); Niccolo′ Righetti, Boise, ID (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Mark A. Helm, Santa Cruz, CA (US); James Fitzpatrick, Laguna Niguel, CA (US); and Ugo Russo, Boise, ID (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 29, 2022, as Appl. No. 17/897,869.
Prior Publication US 2024/0070023 A1, Feb. 29, 2024
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/1435 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
determining, by a processing device, a value of a memory endurance state metric associated with a memory device in a memory sub-system;
determining a target value of a code rate based on the value of the memory endurance state metric; and
adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.