US 11,983,065 B2
Logic based read sample offset in a memory sub-system
Bruce A. Liikanen, Berthoud, CO (US); and Michael Sheperek, Longmont, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 18, 2021, as Appl. No. 17/445,395.
Application 17/445,395 is a continuation of application No. 16/507,500, filed on Jul. 10, 2019, granted, now 11,119,848.
Prior Publication US 2021/0382786 A1, Dec. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1048 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0658 (2013.01); G06F 3/0683 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory system comprising:
one or more memory devices; and
a processing device coupled to the one or more memory devices, wherein the processing device is to:
perform a first exclusive-or (XOR) operation on results from a center read sample and results from a left read sample to obtain a first value;
perform a second XOR operation on the results from the center read sample and results of a right read sample to obtain a second value;
perform a first count operation on the first value to determine a first difference bit count;
perform a second count operation on the second value to determine a second difference bit count; and
determine, based on the first difference bit count and the second difference bit count, a difference bit count.