a plurality of path margin monitor (PMM) circuits that receive (a) functional signals propagating along signal paths in an integrated circuit, and (b) corresponding clock signals used to clock the functional signals; and output PMM signals indicative of path margins for the signal paths, the PMM signals generated from the received functional signals and clock signals; and

a controller that controls the PMM circuits, and receives and analyzes the PMM signals to monitor the path margins across the integrated circuit;

wherein the PMM circuits and the controller are integrated as part of the integrated circuit.