| CPC G01R 31/31727 (2013.01) [G01R 31/31703 (2013.01)] | 20 Claims |
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1. A system comprising:
an integrated circuit (IC) comprising:
at least one semiconductor die comprising:
an oscillator to output a clock signal on a first line;
a switch coupled to the first line;
a voltage divider formed of a first resistor and a second resistor; and
a control circuit to control the switch, wherein the control circuit is to cause the switch to couple the clock signal to the voltage divider in a non-reset mode and to decouple the clock signal from the voltage divider in a reset mode;
a supply voltage pin external to and coupled to the at least one semiconductor die to provide a supply voltage to the IC;
a reset pin external to and coupled to the at least one semiconductor die, the reset pin coupled to the first line to receive a reset signal via the supply voltage pin, wherein in the non-reset mode the clock signal is to be superimposed on the reset signal at the reset pin; and
a monitoring circuit external to and coupled to the IC, wherein the monitoring circuit is to identify presence of the clock signal superimposed on the reset signal at the reset pin.
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