US 11,982,705 B2
Substrate analysis apparatus and substrate analysis method
Youn Gon Oh, Hwaseong-si (KR); Ji Hun Kim, Uiwang-si (KR); Sae Yun Ko, Hwaseong-si (KR); Gil Ho Gu, Hwaseong-si (KR); Dong Su Kim, Hwaseong-si (KR); Eun Hee Lee, Hwaseong-si (KR); Ho Chan Lee, Seoul (KR); Seong Sil Jeong, Incheon (KR); and Seong Pyo Hong, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 9, 2022, as Appl. No. 17/690,317.
Claims priority of application No. 10-2021-0115188 (KR), filed on Aug. 31, 2021.
Prior Publication US 2023/0067060 A1, Mar. 2, 2023
Int. Cl. G01R 31/28 (2006.01); H01L 21/673 (2006.01); H01L 21/677 (2006.01)
CPC G01R 31/2831 (2013.01) [H01L 21/6735 (2013.01); H01L 21/6773 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A substrate analysis apparatus comprising:
an interlayer conveying module which is provided in a first region of the substrate analysis apparatus, and configured to transport a first Front Opening Unified Pod (FOUP) configured to store a plurality of wafers in a vertical direction;
an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer, from among the plurality of wafers, from the first FOUP to a second FOUP provided in a second region of the substrate analysis apparatus different from the first region;
a pre-processing module which is provided in the second region, and configured to form a test wafer piece using the wafer inside the second FOUP;
an analysis module which is provided in the second region, and configured to analyze the test wafer piece; and
a transfer rail which is provided in the second region, and configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece,
wherein the wafer comprises a first identifier indicating information corresponding to the wafer,
the test wafer piece comprises a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and
the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.