US 12,302,767 B2
Buffer layer in memory cell to prevent metal redeposition
Chung-Chiang Min, Zhubei (TW); Chang-Chih Huang, Taichung (TW); Yuan-Tai Tseng, Zhubei (TW); Kuo-Chyuan Tzeng, Chu-Pei (TW); and Yihuei Zhu, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 7, 2022, as Appl. No. 18/076,726.
Application 18/076,726 is a continuation of application No. 17/074,843, filed on Oct. 20, 2020, granted, now 11,532,785.
Prior Publication US 2023/0100433 A1, Mar. 30, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/828 (2023.02) [H10B 63/20 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/245 (2023.02); H10N 70/826 (2023.02); H10N 70/882 (2023.02); H10N 70/883 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first electrode overlying a substrate;
a data storage layer disposed on the first electrode;
a second electrode overlying the data storage layer;
a buffer layer disposed between the data storage layer and the second electrode; and
a metal layer disposed between the buffer layer and the data storage layer, wherein the buffer layer directly contacts the metal layer.