US 12,302,717 B2
Pixel and display device having the same
Keun Woo Kim, Yongin-si (KR); Sang Sub Kim, Yongin-si (KR); Hye Na Kwak, Yongin-si (KR); Doo Na Kim, Yongin-si (KR); Thanh Tien Nguyen, Yongin-si (KR); Yong Su Lee, Yongin-si (KR); and Jae Hwan Chu, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Apr. 24, 2020, as Appl. No. 16/857,888.
Claims priority of application No. 10-2019-0101682 (KR), filed on Aug. 20, 2019.
Prior Publication US 2021/0057502 A1, Feb. 25, 2021
Int. Cl. H10K 59/131 (2023.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3291 (2016.01)
CPC H10K 59/131 (2023.02) [G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2320/0233 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
a pixel disposed on and above a main surface of the substrate and in a display area, the pixel comprising:
a light emitting element, the light emitting element being electrically connected between a first power source and a second power source;
a first transistor electrically connected between the first power source and the light emitting element and controlling a driving current flowing through the light emitting element in response to a voltage of a first node;
a switching transistor electrically connected to the first node and including an active layer, the active layer comprising:
first and second conductive regions spaced apart from each other;
a first channel region and a second channel region spaced apart from each other and disposed between the first and second conductive regions; and
a common conductive region disposed between the first and second channel regions; a conductive pattern that overlaps a center of the common conductive region of the active layer in plan view, the center being a plane within the common conductive region that is equal distant between a first boundary between the conductive pattern and the first channel region and a second boundary between the conductive pattern and the second channel region, plan view being from a direction perpendicular to the main surface of the substrate;
a first gate electrode overlapping the first channel region, and a second gate electrode overlapping the second channel region, the second gate electrode not overlapping the first gate electrode in plan view; and
the conductive pattern does not overlap both of the first and second channel regions.