US 12,302,708 B2
Display device having first, second and third high permittivity insulation layers
Jin Woo Lee, Suwon-si (KR); Jintaek Kim, Yongin-si (KR); Yeonhong Kim, Hwaseong-si (KR); and Pilsuk Lee, Seoul (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Feb. 15, 2024, as Appl. No. 18/443,199.
Application 18/443,199 is a continuation of application No. 17/510,040, filed on Oct. 25, 2021, granted, now 11,910,650.
Application 17/510,040 is a continuation of application No. 16/706,597, filed on Dec. 6, 2019, granted, now 11,158,697, issued on Oct. 26, 2021.
Claims priority of application No. 10-2019-0029545 (KR), filed on Mar. 14, 2019.
Prior Publication US 2024/0196654 A1, Jun. 13, 2024
Int. Cl. H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01); H10K 77/10 (2023.01)
CPC H10K 59/1216 (2023.02) [H10K 59/124 (2023.02); H10K 77/111 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A display device, comprising:
a substrate;
a first active pattern and a second active pattern on the substrate, each of the first active pattern and the second active pattern including an oxide semiconductor;
a first high permittivity insulation layer on the first active pattern, the first high permittivity insulation layer being patterned to overlap the first active pattern;
a first inorganic insulation layer on the first high permittivity insulation layer;
a second high permittivity insulation layer on the first inorganic insulation layer, the second high permittivity insulation layer being patterned to overlap the second active pattern;
a first gate electrode and a second gate electrode on the first inorganic insulation layer and the second high permittivity insulation layer, respectively, the first gate electrode and the second gate electrode overlapping the first active pattern and the second active pattern, respectively;
a second inorganic insulation layer on the first gate electrode and the second gate electrode; and
a third high permittivity insulation layer on the second inorganic insulation layer, the third high permittivity insulation layer being patterned to overlap the first gate electrode.