US 12,302,667 B2
Solid state lighting devices with dielectric insulation and methods of manufacturing
Scott D. Schellhammer, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 25, 2023, as Appl. No. 18/473,605.
Application 15/910,460 is a division of application No. 15/069,262, filed on Mar. 14, 2016, granted, now 9,935,237, issued on Apr. 3, 2018.
Application 15/069,262 is a division of application No. 12/853,014, filed on Aug. 9, 2010, granted, now 9,287,452, issued on Mar. 15, 2016.
Application 18/473,605 is a continuation of application No. 17/568,877, filed on Jan. 5, 2022, granted, now 11,769,854.
Application 17/568,877 is a continuation of application No. 16/553,720, filed on Aug. 28, 2019, granted, now 11,227,972, issued on Jan. 18, 2022.
Application 16/553,720 is a continuation of application No. 15/910,460, filed on Mar. 2, 2018, granted, now 10,439,102, issued on Oct. 8, 2019.
Prior Publication US 2024/0030374 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10H 20/81 (2025.01); H10H 20/01 (2025.01); H10H 20/812 (2025.01); H10H 20/821 (2025.01); H10H 20/825 (2025.01)
CPC H10H 20/8215 (2025.01) [H10H 20/01 (2025.01); H10H 20/812 (2025.01); H10H 20/821 (2025.01); H10H 20/825 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor lighting device, comprising:
a first semiconductor material;
a second semiconductor material;
an active region disposed between the first and second semiconductor materials;
a lattice dislocation extending through the active region and at least partially through the first semiconductor material;
a conductive material over and in contact with the second semiconductor material; and
an insulating material disposed in the lattice dislocation and electrically insulating (1) at least a portion of the first semiconductor material from the second semiconductor material, (2) the conductive material from at least one of the active region and the first semiconductor material, or both,
wherein the lattice dislocation includes sidewalls that are surrounded by at least one of the first semiconductor material, the second semiconductor material, and the active region,
wherein the sidewalls extend from a surface of the second semiconductor material into the active region, and
wherein the conductive material includes (a) a first conductive portion over the second semiconductor material and (b) a second conductive portion between the sidewalls of the lattice dislocation and below an upper surface of the insulating material.