US 12,302,651 B2
Imaging device, manufacturing method thereof, and electronic device
Shunpei Yamazaki, Tokyo (JP); Takayuki Ikeda, Kanagawa (JP); Tetsuya Kakehata, Kanagawa (JP); and Ryo Tokumaru, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/275,795
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Sep. 20, 2019, PCT No. PCT/IB2019/057958
§ 371(c)(1), (2) Date Mar. 12, 2021,
PCT Pub. No. WO2020/058919, PCT Pub. Date Mar. 26, 2020.
Claims priority of application No. 2018-177347 (JP), filed on Sep. 21, 2018.
Prior Publication US 2022/0102419 A1, Mar. 31, 2022
Int. Cl. H10F 39/18 (2025.01); H10F 39/00 (2025.01)
CPC H10F 39/184 (2025.01) [H10F 39/80377 (2025.01); H10F 39/805 (2025.01); H10F 39/8063 (2025.01); H10F 39/811 (2025.01)] 6 Claims
OG exemplary drawing
 
1. An imaging device comprising:
a first layer;
a second layer below the first layer;
a third layer below the second layer;
a fourth layer below the third layer,
wherein the first layer, the second layer, the third layer, and the fourth layer comprise a region where the first layer, the second layer, the third layer, and the fourth layer overlap with each other,
wherein the first layer comprises an optical-filter layer,
wherein the second layer comprises single crystal silicon,
wherein the third layer comprises a device-formation layer,
wherein the fourth layer comprises a support substrate,
wherein the second layer comprises a photoelectric-conversion device whose light-absorption layer is the single crystal silicon,
wherein the photoelectric-conversion device is configured to receive light having passed through the optical-filter layer,
wherein the device-formation layer comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitor,
wherein one electrode of the photoelectric-conversion device is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor,
wherein the one electrode of the capacitor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the device-formation layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises a channel formation region of the first transistor, and
wherein the second oxide semiconductor layer comprises a channel formation region of the third transistor and a channel formation region of the fourth transistor.