US 12,302,642 B2
Integrated circuit and method of forming the same
Kuang-Ching Chang, Hsinchu (TW); Jung-Chan Yang, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); and Kuo-Nan Yang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 1, 2024, as Appl. No. 18/760,500.
Application 18/760,500 is a continuation of application No. 18/363,230, filed on Aug. 1, 2023, granted, now 12,033,998.
Application 18/363,230 is a continuation of application No. 18/066,154, filed on Dec. 14, 2022, granted, now 11,756,952, issued on Sep. 12, 2023.
Application 18/066,154 is a continuation of application No. 17/463,241, filed on Aug. 31, 2021, granted, now 11,552,069, issued on Jan. 10, 2023.
Prior Publication US 2024/0355806 A1, Oct. 24, 2024
Int. Cl. G06F 1/3287 (2019.01); H10D 89/10 (2025.01)
CPC H10D 89/10 (2025.01) [G06F 1/3287 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first power rail and a second power rail on a back-side of a wafer, the first power rail and the second power rail extending in a first direction, the first power rail and the second power rail being separated from each other in a second direction different from the first direction, and the first power rail and the second power rail being configured to supply a first voltage;
a header circuit coupled to the first power rail and the second power rail, and being configured to supply the first voltage to the first power rail and the second power rail;
a third power rail on the back-side of the wafer, the third power rail extending in the first direction and being between the first power rail and the second power rail, and being separated from the first power rail and the second power rail in the second direction, the third power rail being configured to supply a second voltage;
a fourth power rail on a front-side of the wafer opposite from the back-side of the wafer, the fourth power rail including a first set of conductors extending in the second direction, and each conductor of the first set of conductors is separated from one another in the first direction; and
a fifth power rail on the back-side of the wafer, the fifth power rail extending in the first direction, being separated from the first power rail and the second power rail in the second direction, and being separated from the third power rail in the first direction,
wherein the fourth power rail and the fifth power rail are configured to supply a third voltage to the header circuit.