| CPC H10D 86/60 (2025.01) [C23C 14/086 (2013.01); G01N 23/207 (2013.01); G02F 1/1368 (2013.01); H01L 22/12 (2013.01); H10D 30/6755 (2025.01); H10D 30/6756 (2025.01); H10D 62/40 (2025.01); H10D 62/80 (2025.01); H10D 86/423 (2025.01); H10D 99/00 (2025.01); H01L 21/0237 (2013.01); H01L 21/02422 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 2924/0002 (2013.01)] | 15 Claims |

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1. A display device comprising:
a first transistor, a second transistor, a light-emitting element, and a capacitor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor and one electrode of the capacitor,
wherein another electrode of the capacitor is electrically connected to a power supply line,
wherein a potential of the power supply line is supplied to the light-emitting element at least through a channel of the second transistor,
wherein at least one of the first transistor and the second transistor comprises a gate electrode, an oxide semiconductor layer, and a gate insulating film between the gate electrode and the oxide semiconductor layer,
wherein a plurality of circumferentially distributed spots are observable in a nanobeam electron diffraction pattern of the oxide semiconductor layer,
wherein the plurality of circumferentially distributed spots do not have regularity that represents crystal parts aligned with a specific plane,
wherein the oxide semiconductor layer comprises a region in contact with a top surface of an insulating film,
wherein the insulating film comprises silicon oxide, and
wherein the gate insulating film comprises silicon oxide.
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