US 12,302,637 B2
Semiconductor wafer with devices having different top layer thicknesses
Gulbagh Singh, Hisnchu (TW); Kuan-Liang Liu, Hsinchu (TW); Wang Po-Jen, Hsinchu (TW); Kun-Tsang Chuang, Hsinchu (TW); and Hsin-Chi Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 29, 2024, as Appl. No. 18/426,243.
Application 17/827,636 is a division of application No. 16/851,345, filed on Apr. 17, 2020, granted, now 11,348,944, issued on May 31, 2022.
Application 18/426,243 is a continuation of application No. 17/827,636, filed on May 27, 2022, granted, now 11,887,987.
Prior Publication US 2024/0170489 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 86/00 (2025.01); H01L 21/02 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H10D 86/01 (2025.01)
CPC H10D 86/201 (2025.01) [H01L 21/0206 (2013.01); H01L 21/02532 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/31053 (2013.01); H01L 21/76251 (2013.01); H10D 86/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device; and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide.