| CPC H10D 84/856 (2025.01) [H01L 25/074 (2013.01); H10D 84/0172 (2025.01); H10D 84/0195 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01)] | 9 Claims |
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1. A semiconductor structure, comprising:
a substrate;
a first transistor, located on the substrate;
a second transistor, located above the first transistor; and
a gate structure, the gate structure comprising a first gate layer and a second gate layer, which are connected to each other, the first gate layer surrounding the first transistor, and the second gate layer surrounding the second transistor;
wherein an extension direction of a conductive channel of the first transistor and an extension direction of a conductive channel of the second transistor are both perpendicular to the substrate;
a first conductive layer, the first conductive layer being located between the first transistor and the second transistor, wherein a plane in which an extension direction of the first conductive layer is located is parallel to the substrate;
a second conductive layer, the second conductive layer being located in the substrate and connected to the first transistor, wherein a plane in which an extension direction of the second conductive layer is located is parallel to the substrate;
wherein a projection of the first conductive layer on the substrate and a projection of the second conductive layer on the substrate at least partially do not overlap;
wherein the first conductive layer comprises a first segment, a second segment, and a third segment, and two ends of the third segment are connected to the first segment and the second segment respectively, such that a first space is formed on an inner side of the first conductive layer; and
wherein the second conductive layer comprises a fourth segment, a fifth segment, and a sixth segment, and two ends of the sixth segment are connected to the fourth segment and the fifth segment respectively, such that a second space is formed on an inner side of the second conductive layer.
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