US 12,302,632 B2
Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process
Jun Sung Kang, Portland, OR (US); Kai Loon Cheong, Beaverton, OR (US); Erica J. Thompson, Beaverton, OR (US); Biswajeet Guha, Hillsboro, OR (US); William Hsu, Hillsboro, OR (US); Dax M. Crum, Beaverton, OR (US); Tahir Ghani, Portland, OR (US); and Bruce Beattie, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 29, 2023, as Appl. No. 18/523,637.
Application 18/523,637 is a division of application No. 16/146,808, filed on Sep. 28, 2018, granted, now 11,869,891.
Prior Publication US 2024/0096896 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/85 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 62/121 (2025.01); H10D 62/832 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 64/513 (2025.01); H10D 64/693 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a nanowire comprising silicon;
a gate stack around the nanowire, the gate stack comprising a gate dielectric and a gate electrode;
a first dielectric spacer along a first side of the gate stack, and a second dielectric spacer along a second side of the gate stack, the first and second dielectric spacers over at least a portion of the nanowire;
an insulating material vertically between and in contact with the portion of the nanowire and the first and second dielectric spacers; and
a first epitaxial source or drain structure at the first side of the gate stack, and a second epitaxial source or drain structure at the second side of the gate stack.