US 12,302,630 B2
Integrated circuit with backside trench for metal gate definition
Kuo-Cheng Chiang, Hsinchu (TW); Jung-Chien Cheng, Hsinchu (TW); Shi-Ning Ju, Hsinchu (TW); Guan-Lin Chen, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/447,881.
Application 18/447,881 is a division of application No. 17/484,956, filed on Sep. 24, 2021, granted, now 11,855,079.
Claims priority of provisional application 63/182,252, filed on Apr. 30, 2021.
Prior Publication US 2023/0387109 A1, Nov. 30, 2023
Int. Cl. H10D 84/83 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01)
CPC H10D 84/83 (2025.01) [H01L 21/76224 (2013.01); H10D 30/021 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/511 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a substrate;
a first nanosheet transistor over the substrate and having a first gate electrode, a first plurality of stacked channels, and a first dielectric fin structure below the first plurality of stacked channels;
a second nanosheet transistor over the substrate and having a second gate electrode, a second plurality of stacked channels, and a second dielectric fin structure below the second plurality of stacked channels; and
a gate isolation structure between the first nanosheet transistor and the second nanosheet transistor, wherein a bottommost surface of the gate isolation structure is substantially coplanar with a bottommost surface of the first dielectric fin structure.