US 12,302,627 B2
Semiconductor device with non-conformal gate dielectric layers
Yung-Hsiang Chan, Taichung (TW); Wen-Hung Huang, Hsin-Chu (TW); Shan-Mei Liao, Hsinchu (TW); Jian-Hao Chen, Hsinchu (TW); Kuo-Feng Yu, Hsinchu County (TW); and Kuei-Lun Lin, Keelung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 14, 2024, as Appl. No. 18/441,443.
Application 18/441,443 is a continuation of application No. 18/182,959, filed on Mar. 13, 2023, granted, now 11,908,745.
Application 18/182,959 is a continuation of application No. 17/233,098, filed on Apr. 16, 2021, granted, now 11,605,563, issued on Mar. 14, 2023.
Prior Publication US 2024/0186188 A1, Jun. 6, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/0144 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/0135 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/0181 (2025.01)] 20 Claims
OG exemplary drawing
 
16. A method, comprising:
forming a gate dielectric layer having an asymmetric thickness profile surrounding each of a plurality of semiconductor layers of a fin structure extending from a substrate; and
forming a gate electrode over the fin structure and surrounding each of the plurality of semiconductor layers,
wherein the forming of the gate dielectric layer having the asymmetric thickness profile comprises:
introducing a first precursor over the substrate for a first time duration,
performing a first purging process for a second time duration,
introducing a second precursor over the substrate for a third time duration, and
performing a second purging process for a fourth time duration.