US 12,302,626 B2
Asymmetric source/drain epitaxy
Yu-Lien Huang, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 27, 2023, as Appl. No. 18/520,247.
Application 15/996,027 is a division of application No. 15/592,899, filed on May 11, 2017, granted, now 9,991,165, issued on Jun. 5, 2018.
Application 18/520,247 is a continuation of application No. 17/347,064, filed on Jun. 14, 2021, granted, now 11,854,897.
Application 17/347,064 is a continuation of application No. 16/429,657, filed on Jun. 3, 2019, granted, now 11,037,827, issued on Jun. 15, 2021.
Application 16/429,657 is a continuation of application No. 15/996,027, filed on Jun. 1, 2018, granted, now 10,312,145, issued on Jun. 4, 2019.
Claims priority of provisional application 62/427,742, filed on Nov. 29, 2016.
Prior Publication US 2024/0105516 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H10D 84/013 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/0147 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a semiconductor substrate having a first fin and a second fin;
a gate structure extending over the first fin and the second fin;
a first spacer on a first sidewall of the first fin;
a second spacer on a sidewall of the second fin, the second spacer being taller than the first spacer;
a first epitaxy over the first fin on a first side of the gate structure; and
a second epitaxy over the second fin on the first side of the gate structure, the first epitaxy extending higher than the second epitaxy.