| CPC H10D 8/60 (2025.01) [H01L 21/26513 (2013.01); H10D 8/051 (2025.01); H10D 8/411 (2025.01); H10D 62/8325 (2025.01)] | 20 Claims | 

| 
               1. A method, comprising: 
            forming a vertical-conduction electronic power device from a wafer of wide band gap semiconductor having a first conductivity type and a surface, the wafer including a drift region and a plurality of first implanted regions, the plurality of first implanted regions having a second conductivity type and extending in the drift region from the surface, the forming including: 
              forming a plurality of first and second Schottky diodes by forming a plurality of metal portions on the surface, each of the plurality of metal portions being in Schottky contact with the drift region at a plurality of surface portions of the drift region, the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from the second Schottky diodes, the forming of the plurality of metal portions including: 
                forming each of the plurality of metal portions on a respective one of the plurality of first implanted regions, each of the plurality of first implanted regions having an interface with the drift region, each of the plurality of metal portions having edges that are spaced from the interface of each of the plurality of first implanted regions with the drift region, each of the plurality of metal portions being in contact with a respective one of the plurality of first implanted regions and with the drift region. 
                   |