| CPC H10D 64/256 (2025.01) [H10D 62/157 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01)] | 27 Claims |
|
1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region, the second main surface being opposite to the first main surface, the first impurity region constituting at least a portion of the second main surface, the first impurity region having a first conductivity type, the second impurity region constituting at least a portion of the first main surface, the second impurity region being provided in contact with the first impurity region, the second impurity region having a second conductivity type different from the first conductivity type, the third impurity region being provided in contact with the second impurity region so as to be separated from the first impurity region, the third impurity region having the first conductivity type;
a first electrode in contact with each of the second impurity region and the third impurity region on the first main surface;
a gate electrode; and
a second electrode in contact with the first impurity region on the second main surface, wherein
the second impurity region includes a first region and a second region disposed between the first region and the second main surface and in contact with the first region,
an impurity concentration of the first region is more than or equal to 6×1016 cm−3,
when a drain current density is measured while changing a drain voltage under a temperature condition of 25° C. to 175° C., an inclination of the drain current density with respect to the drain voltage becomes smaller as a temperature is increased, and
the second region having a super junction region formed to face the gate electrode.
|