| CPC H10D 64/111 (2025.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 30/0281 (2025.01); H10D 30/655 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01)] | 20 Claims |
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15. A method for forming an integrated chip, comprising:
forming a drain region and a source region within a substrate;
forming a gate structure over the substrate between the source region and the drain region;
depositing a first dielectric layer over the substrate;
forming a plurality of contacts in the first dielectric layer over the source and drain regions and a field plate between the gate structure and the drain region, wherein forming the plurality of contacts and the field plate comprises:
performing a first etch process to form a field plate opening in the first dielectric layer between the gate structure and the drain region;
forming a masking layer over the first dielectric layer, wherein the masking layer at least partially fills the field plate opening;
performing a second etch process on the first dielectric layer according to the masking layer to form a plurality of contact openings in the first dielectric layer;
depositing a conductive material within the field plate opening and the plurality of contact openings;
performing a planarization process on the conductive material; and
forming a plurality of conductive wires over the plurality of contacts.
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