US 12,302,615 B2
Epitaxial structures exposed in airgaps for semiconductor devices
Po-Yu Lin, New Taipei (TW); Wei-Yang Lee, Taipei (TW); Chia-Pin Lin, Hsinchu County (TW); Tzu-Hua Chiu, Hsinchu (TW); Kuan-Hao Cheng, Hsinchu (TW); Wei-Han Fan, Hsin-Chu (TW); Li-Li Su, HsinChu County (TW); and Wei-Min Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 7, 2024, as Appl. No. 18/434,914.
Application 18/434,914 is a division of application No. 17/394,668, filed on Aug. 5, 2021, granted, now 11,923,409.
Claims priority of provisional application 63/168,479, filed on Mar. 31, 2021.
Prior Publication US 2024/0186373 A1, Jun. 6, 2024
Int. Cl. H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 62/116 (2025.01) [H10D 30/031 (2025.01); H10D 30/6757 (2025.01); H10D 64/018 (2025.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/30604 (2013.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a semiconductor substrate;
forming a stack of first semiconductor layers and second semiconductor layers over the semiconductor substrate, the first semiconductor layers and the second semiconductor layers having different material compositions;
forming a gate structure over the stack;
removing portions of the stack on two sides of the gate structure to form source/drain trenches;
removing end portions of the first semiconductor layers to form first gaps between adjacent second semiconductor layers;
forming inner spacers in the first gaps; and
growing source/drain features in the source/drain trenches using a selective epitaxial growth (SEG) process, the SEG process includes a deposition operation and an etching operation, the deposition operation includes depositing silicon using a silicon-containing chemical with a first flow rate, the etching operation includes applying an etchant chemical at a second flow rate, and a ratio of the first flow rate to the second flow rate is greater than 1,
wherein the SEG process includes simultaneously performing the deposition operation and the etch operation, and the SEG process forms air gaps between the source/drain features and the inner spacers, wherein each of the air gaps expose at least half of a sidewall surface of a respective inner spacer of the inner spacers,
wherein the inner spacers include a first inner spacer, a second inner spacer over the first inner spacer, and a third inner spacer over the second inner spacer,
wherein a source/drain feature of the source/drain features includes a first curved surface exposed in a first air gap between the first inner spacer and the source/drain feature, a second curved surface exposed in a second air gap between the second inner spacer and the source/drain feature, and a third curved surface exposed in a third air gap between the third inner spacer and the source/drain feature,
wherein the first curved surface includes an apex at a mid-height of the first air gap, the second curved surface includes an apex at a mid-height of the second air gap, and the third curved surface includes an apex at a mid-height of the third air gap, wherein the third curved surface has a greater curvature than the second curved surface, and the second curved surface has a greater curvature than the first curved surface.