US 12,302,613 B2
Manufacture of robust, high-performance devices
Siddarth Sundaresan, Dulles, VA (US); Ranbir Singh, Dulles, VA (US); and Jaehoon Park, Dulles, VA (US)
Assigned to GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed by GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed on Apr. 28, 2021, as Appl. No. 17/242,650.
Application 17/242,650 is a division of application No. 16/550,249, filed on Aug. 25, 2019, granted, now 11,031,461.
Prior Publication US 2021/0273044 A1, Sep. 2, 2021
Int. Cl. H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01)
CPC H10D 62/102 (2025.01) [H10D 12/031 (2025.01); H10D 30/66 (2025.01); H10D 62/307 (2025.01); H10D 62/8325 (2025.01); H01L 21/0465 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising: forming a silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET); forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; forming a MOSFET channel; and forming a second conductivity type shield region in direct contact with a portion of the MOSFET channel along a surface of a drift layer, wherein a lateral location of highest doping concentration of the second conductivity type shield region is positioned within a boundary of the second conductivity type well region, wherein the second conductivity type shield region is located outside the first conductivity type source region, and wherein the MOSFET is a planar MOSFET.