US 12,302,612 B2
And manufacture of robust, high-performance devices
Siddarth Sundaresan, Dulles, VA (US); Ranbir Singh, Dulles, VA (US); and Jaehoon Park, Dulles, VA (US)
Assigned to GeneSIC Semiconductor Inc., Dulles, VA (US)
Filed by GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed on Apr. 15, 2021, as Appl. No. 17/231,301.
Application 17/231,301 is a continuation of application No. 16/550,249, filed on Aug. 25, 2019, granted, now 11,031,461.
Prior Publication US 2021/0257447 A1, Aug. 19, 2021
Int. Cl. H10D 62/10 (2025.01); H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01)
CPC H10D 62/102 (2025.01) [H10D 12/031 (2025.01); H10D 30/66 (2025.01); H10D 62/307 (2025.01); H10D 62/8325 (2025.01); H01L 21/0465 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device comprising a unit cell on a silicon carbide (SiC) substrate, the unit cell comprising:
a first conductivity type source region;
a second conductivity type well region; and
a second conductivity type shield region located within a metal-oxide-semiconductor field-effect transistor (MOSFET) channel,
wherein the second conductivity type shield region in direct contact with the metal-oxide-semiconductor field-effect transistor (MOSFET) channel and located closer to one of an edge of the second conductivity type well region and an edge of the first conductivity type source region along a first surface of a drift layer,
wherein the second conductivity type shield region is confined within the second conductivity type well region, and
wherein the device is a planar metal oxide semiconductor field-effect transistor (MOSFET).