US 12,302,611 B2
FinFET structure with a composite stress layer and reduced fin buckling
Wei-Jen Lai, Keelung (TW); Yen-Ming Chen, Hsin-Chu County (TW); and Tsung-Lin Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 28, 2023, as Appl. No. 18/521,584.
Application 17/113,955 is a division of application No. 16/414,565, filed on May 16, 2019, granted, now 10,861,969, issued on Dec. 8, 2020.
Application 18/521,584 is a continuation of application No. 17/876,330, filed on Jul. 28, 2022, granted, now 11,855,207.
Application 17/876,330 is a continuation of application No. 17/113,955, filed on Dec. 7, 2020, granted, now 11,411,107, issued on Aug. 9, 2022.
Claims priority of provisional application 62/698,357, filed on Jul. 16, 2018.
Prior Publication US 2024/0097033 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/69 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/792 (2025.01) [H01L 21/0217 (2013.01); H01L 21/02211 (2013.01); H01L 21/02271 (2013.01); H01L 21/28088 (2013.01); H01L 21/76224 (2013.01); H10D 30/751 (2025.01); H10D 62/115 (2025.01); H10D 64/667 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
an active region formed on a semiconductor substrate;
a gate stack disposed on the active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; and
a composite stress layer interposed between the active region and the gate dielectric layer, wherein the composite stress layer includes a first silicon nitride layer and a second silicon nitride layer on the first silicon nitride layer, the first silicon nitride layer having a first compressive stress and the second silicon nitride layer having a second compressive stress greater than the first compressive stress.