| CPC H10D 30/694 (2025.01) [H10D 30/68 (2025.01); H10D 30/6891 (2025.01); H10D 30/69 (2025.01)] | 12 Claims |
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1. A semiconductor device comprising:
a semiconductor substrate;
a first laminated pattern formed of a first gate dielectric film formed on an upper surface of the semiconductor substrate, a first gate electrode formed on the first gate dielectric film, and a first dielectric film formed on the first gate electrode;
a second gate dielectric film formed on the upper surface of the semiconductor substrate and on a side surface of the first laminated pattern, the second gate dielectric film including a charge storage portion;
a second gate electrode formed on the second gate dielectric film so as to be adjacent to the first gate electrode;
a first silicide layer formed on an upper surface of the second gate electrode; and
a first source region and a first drain region each formed in the semiconductor substrate exposed from the first laminated pattern and the second gate electrode,
wherein each of the first gate electrode and the second gate electrode is formed of a semiconductor film,
wherein each of the first source region and the first drain region has a first conductivity type first semiconductor region, and a first conductivity type second semiconductor region having a higher impurity concentration than the first semiconductor region,
wherein an upper surface of the first gate electrode is lower than the highest position of a lower surface of the first silicide layer, and
wherein a difference between the upper surface of the first gate electrode and the highest position of an upper surface of the first silicide layer is equal to or larger than a depth of the second semiconductor region.
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