| CPC H10D 30/6757 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H10B 20/00 (2023.02); H10B 20/25 (2023.02); H10D 30/031 (2025.01); H10D 30/673 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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8. A method, comprising:
forming a first transistor and a second transistor over a substrate and electrically connected to each other, wherein each of the first and second transistors comprises:
first semiconductor layers and second semiconductor layers alternately stacked over the substrate;
a gate structure crossing the first semiconductor layers and the second semiconductor layers, wherein in a cross-sectional view where the gate structure crosses the first semiconductor layers and the second semiconductor layers, the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers; and
source/drain structures on opposite sides of the gate structure;
forming a first word line electrically connected to the gate structure of the first transistor;
forming a second word line electrically connected to the gate structure of the second transistor; and
forming a bit line electrically connected to a first one of the source/drain structures of the first transistor.
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