US 12,302,608 B2
Nanowire transistor and method for fabricating the same
Po-Kuang Hsieh, Kaohsiung (TW); Shih-Hung Tsai, Tainan (TW); Ching-Wen Hung, Tainan (TW); and Chun-Hsien Lin, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on May 31, 2024, as Appl. No. 18/679,459.
Application 18/679,459 is a continuation of application No. 18/201,769, filed on May 25, 2023, granted, now 12,027,600.
Application 18/201,769 is a continuation of application No. 17/185,985, filed on Feb. 26, 2021, granted, now 11,705,498, issued on Jul. 18, 2023.
Claims priority of application No. 202110101854.9 (CN), filed on Jan. 26, 2021.
Prior Publication US 2024/0321993 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/80 (2025.01); H10D 62/83 (2025.01); H10D 64/62 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/01 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/8303 (2025.01); H10D 62/882 (2025.01); H10D 64/62 (2025.01)] 5 Claims
OG exemplary drawing
 
1. A nanowire transistor, comprising:
a channel structure on a substrate;
a gate structure on and around the channel structure;
a source/drain structure adjacent to two sides of the gate structure, wherein the source/drain structure comprises graphene; and
a contact plug connected to the source/drain structure, wherein the contact plug comprises:
a silicide layer on the source/drain structure;
a graphene layer on the silicide layer; and
a barrier layer on the graphene layer.