US 12,302,607 B2
Backside gate contact
Huan-Chieh Su, Changua County (TW); Chun-Yuan Chen, HsinChu (TW); Lo-Heng Chang, Hsinchu (TW); Li-Zhen Yu, New Taipei (TW); Lin-Yu Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 21, 2024, as Appl. No. 18/670,132.
Application 18/670,132 is a continuation of application No. 18/321,620, filed on May 22, 2023, granted, now 11,996,461.
Application 18/321,620 is a continuation of application No. 17/228,955, filed on Apr. 13, 2021, granted, now 11,658,226, issued on May 23, 2023.
Claims priority of provisional application 63/151,228, filed on Feb. 19, 2021.
Prior Publication US 2024/0304695 A1, Sep. 12, 2024
Int. Cl. H10D 30/67 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first plurality of nanostructures disposed over a backside dielectric layer;
a first gate structure wrapping around each of the first plurality of nanostructures;
a second plurality of nanostructures disposed over a backside gate contact;
a second gate structure wrapping around each of the second plurality of nanostructures; and
an isolation structure disposed between the backside dielectric layer and the backside gate contact along a first direction,
wherein the backside gate contact is spaced apart from the isolation structure by a liner.