| CPC H10D 30/6713 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/118 (2025.01); H10D 62/80 (2025.01); H10D 62/832 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10B 10/125 (2023.02)] | 20 Claims |
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1. A semiconductor device, comprising:
a first gate structure formed over a first fin in a first region of a substrate and a first source/drain feature adjacent to the first gate structure; and
a second gate structure formed over a second fin in a second region of the substrate and a second source/drain feature adjacent to the second gate structure;
wherein the first fin includes a first plurality of semiconductor channel layers interposed by a first plurality of inner spacers, the first plurality of semiconductor channel layers and the first plurality of inner spacers collectively defining a first sidewall surface;
wherein the second fin includes a second plurality of semiconductor channel layers interposed by a second plurality of inner spacers, the second plurality of semiconductor channel layers and the second plurality of inner spacers collectively defining a second sidewall surface;
wherein a first continuous adhesion layer interposes, and is in contact with, each of the first source/drain feature and the first sidewall surface; and
wherein a second continuous adhesion layer interposes, and is in contact with, each of the second source/drain feature and the second sidewall surface.
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