| CPC H10D 30/63 (2025.01) [H10D 30/6735 (2025.01); H10D 62/119 (2025.01); H10D 64/205 (2025.01); H10D 64/252 (2025.01)] | 6 Claims |
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1. A semiconductor device comprising:
a plurality of column portions including a semiconductor,
the plurality of column portions each including:
a source region;
a drain region; and
a channel formation region located between the source region and the drain region,
the semiconductor device further comprising:
a gate electrode provided, via an insulating layer, at a side wall of the channel formation region of each of the plurality of column portions and configured to control a current between the source region and the drain region;
a first semiconductor layer coupled to the source region of each of the plurality of column portions;
a first metal layer coupled to the first semiconductor layer;
a second semiconductor layer coupled to the drain region of each of the plurality of column portions; and
a second metal layer coupled to the second semiconductor layer, wherein
a thickness of the drain region is greater than a thickness of the source region, and an impurity concentration of the semiconductor included in the drain region is lower than an impurity concentration of the semiconductor included in the source region.
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