CPC H10D 30/6219 (2025.01) [H01L 21/28518 (2013.01); H01L 21/76805 (2013.01); H01L 21/76862 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 62/151 (2025.01); H10D 64/62 (2025.01)] | 20 Claims |
1. A semiconductor device, comprising:
a fin structure extending above a substrate;
a source/drain region in the fin structure;
a first inter-layer dielectric (ILD) layer over the source/drain region;
a first contact plug extending through the first ILD layer to a silicide region of the source/drain region, wherein the first contact plug comprises:
a metallic fill layer; and
a conductive barrier layer conformally surrounding a bottom portion of the metallic fill layer, wherein the conductive barrier layer has a material different from a material of the metallic fill layer, and a topmost surface of the conductive barrier layer is lower than a topmost surface of a non-linear top surface of the metallic fill layer;
a second contact plug over the first contact plug, wherein the metallic fill layer of the first contact plug has a protruding portion extending above the first ILD layer and laterally surrounding a lower part of the second contact plug; and
a second ILD layer over the first ILD layer, wherein the protruding portion of the metallic fill layer of the first contact plug is in contact with a sidewall of the second ILD layer, wherein the second contact plug has a bottom surface lower than a bottom surface of the second ILD layer, an outer sidewall of the first contact plug is aligned with an outer sidewall of the second contact plug.
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