US 12,302,598 B2
Semiconductor device and method of manufacturing the same
Zilan Li, Guangdong (CN)
Assigned to GUANGDONG ZHINENG TECHNOLOGIES, CO. LTD., Guangdong (CN)
Appl. No. 17/603,298
Filed by GUANGDONG ZHINENG TECHNOLOGIES, CO. LTD., Guangdong (CN)
PCT Filed Jan. 17, 2020, PCT No. PCT/CN2020/072766
§ 371(c)(1), (2) Date Oct. 12, 2021,
PCT Pub. No. WO2020/207098, PCT Pub. Date Oct. 15, 2020.
Claims priority of application No. 201910291624.6 (CN), filed on Apr. 12, 2019.
Prior Publication US 2022/0199819 A1, Jun. 23, 2022
Int. Cl. H01L 29/778 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/40 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/475 (2025.01) [H10D 30/015 (2025.01); H10D 62/117 (2025.01); H10D 62/405 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a groove, wherein at least a part of a sidewall of the groove is a (111) plane of Si, a (0001) plane of sapphire Al2O3, a (0001) or (000-1) plane of SiC, or a (0001) or (000-1) plane of intrinsic GaN;
a first channel layer positioned within the groove;
a first barrier layer positioned within the groove, wherein a first heterojunction having a vertical interface is included between the first channel layer and the first barrier layer and a 2DEG or 2DHG is formed in the first heterojunction;
a second channel layer and a second barrier layer, wherein a second heterojunction having a vertical interface is included between the second channel layer and the second barrier layer and a 2DEG or 2DHG is formed in the second heterojunction; and
a screening layer between the first channel layer or the first barrier layer and the second channel layer or the second barrier layer.