| CPC H10D 30/0215 (2025.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01)] | 20 Claims |
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1. A method comprising:
forming a dummy gate stack over a semiconductor region;
forming gate spacers on opposing sides of the dummy gate stack;
forming a source/drain region on a side of the dummy gate stack;
forming a first inter-layer dielectric over the source/drain region;
replacing the dummy gate stack with a replacement gate stack;
recessing the replacement gate stack to form a recess between the gate spacers;
depositing a liner extending into the recess;
depositing a masking layer over the liner and extending into the recess;
forming an etching mask covering a portion of the masking layer;
etching the first inter-layer dielectric to form a source/drain contact opening, wherein the source/drain region is underlying and exposed to the source/drain contact opening;
forming a source/drain contact plug in the source/drain contact opening; and
forming a gate contact plug extending between the gate spacers and electrically connecting to the replacement gate stack.
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