US 12,302,589 B2
Trench capacitor structure with hybrid filling layer
Larry Buffle, Grenoble (FR); Frédéric Voiron, Barraux (FR); and Sophie Archambault, Grenoble (FR)
Assigned to MURATA MANUFACTURING CO., LTD., Nagaokakyo (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Mar. 4, 2024, as Appl. No. 18/594,215.
Application 18/594,215 is a continuation of application No. 17/831,050, filed on Jun. 2, 2022, granted, now 11,955,568.
Claims priority of application No. 21305761 (EP), filed on Jun. 4, 2021.
Prior Publication US 2024/0213377 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 1/66 (2025.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01)
CPC H10D 1/665 (2025.01) [H10D 1/042 (2025.01); H10D 1/696 (2025.01); H10D 1/716 (2025.01)] 7 Claims
OG exemplary drawing
 
1. A capacitor structure, comprising:
a silicon substrate having a trench structure formed therein;
a dielectric layer disposed over a surface of the trench structure, conformal to said surface of the trench structure; and
a filling layer disposed over the dielectric layer and into the trench structure, the filling layer comprising:
a conductive layer; and
a polymer layer,
wherein the conductive layer is disposed between the dielectric layer and the polymer layer, and
wherein a trench depth of the trench structure ranges between 10 and 100 microns, an aspect ratio of the trench structure ranges between 1:10 and 1:60, a thickness of the dielectric layer ranges between 0.6 and 1.5 microns, a thickness of the conductive layer ranges between 10 and 500 nanometers, and a thickness of the polymer layer ranges between 150 and 2000 nanometers.