US 12,302,584 B2
Embedded ferroelectric memory in high-k first technology
Wei Cheng Wu, Zhubei (TW); and Pai Chi Chou, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,216.
Application 18/358,216 is a continuation of application No. 17/230,191, filed on Apr. 14, 2021, granted, now 11,751,400.
Application 17/230,191 is a continuation of application No. 16/428,229, filed on May 31, 2019, granted, now 11,004,867, issued on May 11, 2021.
Claims priority of provisional application 62/691,072, filed on Jun. 28, 2018.
Prior Publication US 2023/0371271 A1, Nov. 16, 2023
Int. Cl. H01L 27/1159 (2017.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/30 (2023.01)
CPC H10B 51/30 (2023.02) [H01L 21/76224 (2013.01); H01L 29/0657 (2013.01); H01L 29/42364 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09)] 20 Claims
OG exemplary drawing
 
1. An integrated chip structure, comprising:
a first doped region and a second doped region disposed within a recessed upper surface of a substrate;
a ferroelectric material arranged over the recessed upper surface of the substrate and between the first doped region and the second doped region; and
an isolation structure arranged within the substrate along a first side of the ferroelectric material, wherein a part of the isolation structure that is vertically below the recessed upper surface of the substrate is asymmetric about a line bisecting a bottommost surface of the isolation structure.