US 12,302,583 B2
3D ferroelectric memory
Sheng-Chih Lai, Hsinchu County (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/353,954.
Application 17/854,701 is a division of application No. 16/903,545, filed on Jun. 17, 2020, granted, now 11,411,025, issued on Aug. 9, 2022.
Application 18/353,954 is a continuation of application No. 17/854,701, filed on Jun. 30, 2022, granted, now 11,770,935.
Claims priority of provisional application 62/924,736, filed on Oct. 23, 2019.
Prior Publication US 2023/0363171 A1, Nov. 9, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/40111 (2019.08); H01L 29/66666 (2013.01); H01L 29/6684 (2013.01); H01L 29/7827 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02); H10B 51/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first semiconductor channel;
a first source/drain region directly over the first semiconductor channel;
a second semiconductor channel directly over the first source/drain region and the first semiconductor channel;
a gate electrode bordering the first semiconductor channel and the second semiconductor channel, wherein the gate electrode extends continuously from laterally adjacent the first semiconductor channel to laterally adjacent the second semiconductor channel; and
a ferroelectric layer separating the gate electrode from the first semiconductor channel;
wherein the gate electrode has a first width at a first elevation level with the first source/drain region and a second width at a second elevation level with the second semiconductor channel, and wherein the second width is greater than the first width.