US 12,302,582 B2
Semiconductor memory device
Hidenobu Nagashima, Yokkaichi Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Apr. 23, 2024, as Appl. No. 18/643,260.
Application 18/643,260 is a continuation of application No. 18/348,826, filed on Jul. 7, 2023, granted, now 12,016,184.
Application 18/348,826 is a continuation of application No. 18/148,924, filed on Dec. 30, 2022, granted, now 11,871,578, issued on Jan. 9, 2024.
Application 18/148,924 is a continuation of application No. 17/184,094, filed on Feb. 24, 2021, granted, now 11,610,912, issued on Mar. 21, 2023.
Application 17/184,094 is a continuation of application No. 16/834,472, filed on Mar. 30, 2020, granted, now 10,971,512, issued on Apr. 6, 2021.
Application 16/834,472 is a continuation of application No. 16/124,553, filed on Sep. 7, 2018, granted, now 10,651,190, issued on May 12, 2020.
Claims priority of application No. 2018-052449 (JP), filed on Mar. 20, 2018.
Prior Publication US 2024/0276732 A1, Aug. 15, 2024
Int. Cl. H10B 43/50 (2023.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H01L 21/311 (2006.01)
CPC H10B 43/50 (2023.02) [H01L 21/76224 (2013.01); H01L 21/76805 (2013.01); H01L 23/535 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a stacked body provided above a substrate, in which conductive layers are isolated from each other and stacked along a first direction crossing a surface of the substrate;
a source layer provided between the substrate and the stacked body;
memory pillars passing through the stacked body along the first direction and being coupled to the source layer;
a first insulation film provided above the stacked body, the first insulation film being located higher than upper surfaces of the memory pillars in the first direction;
isolation portions passing through the stacked body and the first insulation film along the first direction, extending in a second direction crossing the first direction and isolating the stacked body in a third direction crossing the first direction and the second direction;
a first member including silicon and nitrogen provided above the first insulation film;
a second member including silicon and nitrogen provided on side walls of the isolation portions;
first contacts passing through the first insulation film and the first member along the first direction and being coupled to the memory pillars respectively;
through contacts provided in holes formed through the first insulation film and the stacked body along the first direction within a region between two isolation portions adjacent in the third direction among the isolation portions; and
a lower interconnect provided between the substrate and the source layer,
a first through contact of the through contacts being provided in one hole of the holes, the first through contact having a side wall insulation layer provided on a side wall of the one hole and any through contact other than the first through contact being not provided in the one hole, and
one end of the first through contact being electrically connected to the lower interconnect while the first through contact being electrically insulated from the source layer.