US 12,302,581 B2
Semiconductor memory device and method of manufacturing the same
Kyungmin Jang, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 28, 2023, as Appl. No. 18/398,378.
Application 18/398,378 is a continuation of application No. 17/869,826, filed on Jul. 21, 2022, granted, now 11,903,212.
Application 17/869,826 is a continuation of application No. 16/797,285, filed on Feb. 21, 2020, granted, now 11,430,803, issued on Aug. 30, 2022.
Claims priority of application No. 2019-166165 (JP), filed on Sep. 12, 2019.
Prior Publication US 2024/0130135 A1, Apr. 18, 2024
Int. Cl. H10B 43/40 (2023.01); H01L 21/02 (2006.01); H10B 43/27 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 21/0217 (2013.01); H01L 21/02266 (2013.01); H01L 21/02271 (2013.01); H10B 43/27 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a semiconductor substrate;
a transistor disposed on the semiconductor substrate;
a stacked body disposed above the transistor, the stacked body including a plurality of first conductive layers stacked in a first direction, a pillar extending through the plurality of first conductive layers in the first direction and containing a semiconductor layer, and a charge storage film disposed between the plurality of first conductive layers and the semiconductor layer;
a first silicon nitride layer and a second silicon nitride layer disposed above the transistor; and
a conductor extending through the first silicon nitride layer, the second silicon nitride layer, and the plurality of first conductive layers in the first direction and electrically connected to the transistor, wherein
an etching rate of the second silicon nitride layer is different from an etching rate of the first silicon nitride layer.