US 12,302,580 B2
Semiconductor devices and data storage systems including the same
Sanghun Chun, Suwon-si (KR); Jihwan Kim, Suwon-si (KR); Shinhwan Kang, Suwon-si (KR); and Jeehoon Han, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 15, 2021, as Appl. No. 17/231,600.
Claims priority of application No. 10-2020-0100043 (KR), filed on Aug. 10, 2020.
Prior Publication US 2022/0045084 A1, Feb. 10, 2022
Int. Cl. H10B 43/50 (2023.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a peripheral circuit structure including a first substrate and active or passive circuits on the first substrate;
a memory cell structure including (A) a second substrate on the peripheral circuit structure and having a first region and a second region, (B) gate electrodes stacked on the first region to be spaced apart from each other in a first direction and extending on the second region in a second direction, the gate electrodes in a staircase shape, (C) interlayer insulating layers stacked alternately with the gate electrodes, (D) channel structures penetrating through the gate electrodes, the channel structures extending in the first direction, each of the channel structures including a channel layer, and (E) separation regions penetrating through the gate electrodes, the separation regions extending in the second direction and spaced apart from each other in a third direction, wherein the semiconductor device has a through-wiring region including (A) sacrificial insulating layers parallel to the gate electrodes in the second region and alternately stacked with the interlayer insulating layers, and (B) a through-contact plug electrically connecting the gate electrodes with the active or passive circuits; and
a barrier structure surrounding the through-wiring region and having an internal side surface having projections
wherein the barrier structure includes a first barrier layer, a second barrier layer, and a third barrier layer, and the first barrier layer includes a material different from a material of the sacrificial insulating layers.