| CPC H10B 43/40 (2023.02) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
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1. A method of fabricating semiconductor memory device, the method comprising:
forming a peripheral circuit structure on a substrate;
forming a semiconductor layer on the peripheral circuit structure;
forming a mold structure on the semiconductor layer, the mold structure including insulating layers and sacrificial layers that are alternately stacked on the semiconductor layer;
forming an interlayered insulating layer covering the mold structure;
forming a first hole, a second hole and a third hole, the first hole and the second hole penetrating the mold structure, the third hole penetrating the interlayered insulating layer, the first to third holes being formed together through a first anisotropic etching process;
forming a vertical channel structure in the first hole;
replacing the sacrificial layers into electrodes through the second hole;
forming a separation structure in the second hole; and
forming a through contact in the third hole, the through contact electrically connected to the peripheral circuit structure.
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