US 12,302,578 B2
Non-volatile memory device
Moorym Choi, Yongin-si (KR); Jungtae Sung, Seoul (KR); and Yunsun Jang, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 8, 2022, as Appl. No. 17/834,977.
Claims priority of application No. 10-2021-0148537 (KR), filed on Nov. 2, 2021.
Prior Publication US 2023/0140000 A1, May 4, 2023
Int. Cl. H10B 43/40 (2023.01); H01L 23/528 (2006.01); H10B 43/27 (2023.01); H10D 64/23 (2025.01)
CPC H10B 43/40 (2023.02) [H01L 23/5283 (2013.01); H10B 43/27 (2023.02); H10D 64/251 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first gate electrode structure on a first substrate including a cell region and a peripheral circuit region surrounding the cell region, the first gate electrode structure including first gate electrodes spaced apart from each other on the cell region of the first substrate in a first direction substantially perpendicular to an upper surface of the first substrate, and each of the first gate electrodes extending lengthwise in a second direction substantially parallel to the upper surface of the first substrate;
a first channel extending in the first direction through at least a portion of the first gate electrode structure;
a first transistor on the peripheral circuit region of the first substrate;
a second gate electrode structure on the first gate electrode structure and the first transistor, the second gate electrode structure including second gate electrodes spaced apart from each other in the first direction, and each of the second gate electrodes extending lengthwise in the second direction;
a second channel extending in the first direction through at least a portion of the second gate electrode structure;
a second transistor and a third transistor on the second gate electrode structure; and
a second substrate on the second and third transistors,
wherein the first and second channels do not directly contact each other, but are electrically connected with each other, and receive electrical signals from the second transistor, and
wherein the first and third transistors apply electrical signals to the first and second gate electrode structures.