US 12,302,577 B2
Semiconductor device and method of manufacturing the semiconductor device
Jae Seok Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 1, 2022, as Appl. No. 17/683,701.
Claims priority of application No. 10-2021-0121617 (KR), filed on Sep. 13, 2021.
Prior Publication US 2023/0084756 A1, Mar. 16, 2023
Int. Cl. H10B 43/40 (2023.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 43/10 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first source layer spaced apart from a substrate and overlapping with a cell region of the substrate;
a second source layer spaced apart from the substrate and overlapping with a discharge contact region of the substrate;
a cell stack including cell interlayer insulating layers and conductive patterns alternately stacked on the first source layer; and
a channel structure passing through the cell stack and extending into the first source layer,
wherein the channel structure includes an upper channel structure passing through the cell stack and a lower channel structure disposed below the cell stack, and
a connection portion of the upper channel structure and the lower channel structure has a bottleneck pattern.