US 12,302,576 B2
Integrated circuit device and electronic system including the same
Jeeyong Kim, Hanam-si (KR); Junghwan Lee, Seoul (KR); and Hwanyeol Park, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 17, 2022, as Appl. No. 17/648,134.
Claims priority of application No. 10-2021-0021137 (KR), filed on Feb. 17, 2021.
Prior Publication US 2022/0262819 A1, Aug. 18, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/40 (2023.02) [H01L 24/08 (2013.01); H01L 25/0652 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H01L 2224/08147 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a semiconductor substrate having a cell region and a dummy region outside the cell region;
a plurality of gate electrodes and a plurality of insulating layers, in the cell region, extending in first and second directions parallel to a main surface of the semiconductor substrate and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first and second directions crossing each other;
a plurality of dummy mold layers and a plurality of dummy insulating layers alternately stacked in the dummy region in the third direction;
a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the cell region; and
a plurality of dummy structures passing through the plurality of dummy mold layers and the plurality of dummy insulating layers in the dummy region,
wherein the plurality of dummy mold layers are arranged at a same level as the plurality of gate electrodes in the third direction,
wherein the plurality of dummy insulating layers are arranged at a same level as the plurality of insulating layers in the third direction, and
wherein a carbon concentration of an upper dummy mold layer of the plurality of dummy mold layers is less than a carbon concentration of a lower dummy mold layer of the plurality of dummy mold layers, the lower dummy mold layer being between the upper dummy mold layer and the main surface of the semiconductor substrate.