| CPC H10B 43/35 (2023.02) | 20 Claims |
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1. A memory device, comprising:
a first bit line configured to supply a first bit line bias voltage;
a memory cell transistor having a first operating voltage;
a selection transistor having a second operating voltage, and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor,
wherein a drain of the selection transistor is connected to the first bit line; and
a second bit line connected to a drain of the memory cell transistor,
wherein a level of the first operating voltage is about equal to a level of the second operating voltage.
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