US 12,302,574 B2
Semiconductor memory device and method for fabricating the same
Young Rok Kim, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Jun. 14, 2021, as Appl. No. 17/347,195.
Claims priority of application No. 10-2021-0016744 (KR), filed on Feb. 5, 2021.
Prior Publication US 2022/0254792 A1, Aug. 11, 2022
Int. Cl. H10B 43/35 (2023.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/35 (2023.02) [H01L 23/528 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a gate electrode stack vertically stacked over a substrate with bent gate pads, the bent gate pads of the gate electrode stack having a step-shaped structure;
an inter-layer dielectric layer covering the bent gate pads; and
a plurality of contact plugs respectively coupled to the bent gate pads by penetrating the inter-layer dielectric layer,
wherein the bent gate pads include angled corner portions of different sizes in a plan view, the sizes of the angled corner portions progressively changing based on a depth of the bent gate pads in a cross-sectional view,
wherein the inter-layer dielectric layer is seam-free due to the angled corner portions.